1. Field
The following description relates to a scheduler of a reconfigurable array, a method of scheduling commands, a computing apparatus, and a technique for increasing loop operating speed when a loop operation is performed using a reconfiguration array.
2. Description of the Related Art
In general, a reconfigurable architecture refers to a changeable architecture that enables a hardware constitution of a computing apparatus to be optimized when executing a task.
When a task is processed by hardware, while processing speed may be relatively faster than processing by software, due to the fixed nature of the hardware, it is difficult to process the task when the task is changed. When a task is processed by software, while the software may be changed to meet the change in task, it typically exhibits inferior speed compared to processing by hardware.
A reconfigurable architecture has attracted considerable attention in the field of processing a digital signal, for example, in which the same task is repeatedly performed, because such architecture may potentially provide the benefits typically associated with hardware and software.
Meanwhile, digital signal processing procedures may be characterized by inclusion of multiple loop operation processes in which the same operation is repeatedly performed. In general, loop level parallelism (LLP) is often used in order to enhance the loop operating speed. A typical example of the LLP may include software pipelining.
Software pipelining utilizes the principle that operations included in different loop bodies may be performed, simultaneously, if the loop bodies are independent from each other. When the software pipelining is combined with a reconfigurable array, improved performance may be exhibited. For example, operations that may be processed in a parallel manner may be processed simultaneously in each processing unit constituting the reconfigurable array.
However, it is difficult to apply the software pipelining for loop acceleration due to a structure of the reconfigurable array (limited resources) and dependency between loop iterations (limited recurrence). That is, assigning and scheduling the resources of the reconfigurable array is in order to improve the loop operating speed may be an issue.